The present invention is related in general to the field of electronic systems and semiconductor devices and more specifically to automated systems and methods for modeling integrated circuit characteristics for preventing destructive electrostatic discharge and latch-up.
Integrated circuits (ICs) may be severely damaged by electrostatic discharge (ESD) events. A major source of ESD exposure to ICs is from the charged human body (xe2x80x9cHuman Body Modelxe2x80x9d, HBM); the discharge of the human body generates peak currents of several amperes to the IC for about 100 ns. A second source of ESD is from metallic objects (xe2x80x9cMachine Modelxe2x80x9d, MM); it can generate transients with significantly higher rise times than the HBM ESD source. A third source is described by the xe2x80x9cCharged Device Modelxe2x80x9d (CDM), in which the IC itself becomes charged and discharges to ground in the opposite direction than the HBM and MM ESD sources. More detail on ESD phenomena and approaches for protection in ICs can be found in A. Amerasekera and C. Duvvury, xe2x80x9cESD in Silicon Integrated Circuitsxe2x80x9d (John Wiley and Sons LTD. London 1995), and C. Duvvury, xe2x80x9cESD: Design for IC Chip Quality and Reliabilityxe2x80x9d (Int. Symp. Quality in El. Designs, 2000, pp. 251-259; references of recent literature).
ESD phenomena in ICs are growing in importance as the demand for higher operating speed, smaller operating voltages, higher packing density and reduced cost drives a reduction of all device dimensions. This generally implies thinner dielectric layers, higher doping levels with more abrupt doping transitions, and higher electric fieldsxe2x80x94all factors that contribute to an increased sensitivity to damaging ESD events.
The most common protection schemes used in metal-oxide-semiconductor (MOS) ICs rely on the parasitic bipolar transistor associated with an NMOS device whose drain is connected to the pin to be protected and whose source is tied to ground. The protection level or failure threshold can be set by varying the NMOS device width from the drain to the source under the gate oxide of the NMOS device. Under stress conditions, the dominant current conduction path between the protected pin and ground involves the parasitic bipolar transistor of that NMOS device. This parasitic bipolar transistor operates in the snapback region under pin positive with respect to ground stress events.
The dominant failure mechanism, found in the NMOS protection device operating as a parasitic bipolar transistor in snapback conditions, is the onset of second breakdown. Second breakdown is a phenomenon that induces thermal runaway in the device wherever the reduction of the impact ionization current is offset by the thermal generation of carriers. Second breakdown is initiated in a device under stress as a result of self-heating. The peak NMOS device temperature, at which second breakdown is initiated, is known to increase with the stress current level.
Many circuits have been proposed and implemented for protecting ICs from ESD. One method that is used to improve ESD protection for ICs is biasing the substrate of ESD protection circuits on an IC. Other solutions offered in known technology require additional IC elements, silicon real estate, and/or process steps (especially photomask alignment steps). Their fabrication is, therefore, expensive. Examples of device structures and methods are described in U.S. Pat. No. 5,539,233, issued Jul. 23, 1996 (Amerasekera et al., xe2x80x9cControlled Low Collector Breakdown Voltage Vertical Transistor for ESD Protection Circuitsxe2x80x9d); U.S. Pat. No. 5,793,083, issued Aug. 11, 1998 (Amerasekera et al., xe2x80x9cMethod for Designing Shallow Junction, Salicided NMOS Transistors with Decreased Electrostatic Discharge Sensitivityxe2x80x9d); U.S. Pat No. 5,940,258, issued Aug. 17, 1999 (Duvvury, xe2x80x9cSemiconductor ESD Protection Circuitxe2x80x9d); U.S. Pat. No. 6,137,144, issued Oct. 24, 2000, and U.S. Pat. No. 6,143,594, issued Nov. 7, 2000 (Tsao et al, xe2x80x9cOn-Chip ESD Protection in Dual Voltage CMOS); and U.S. patent application Ser. No. 09/456,036, filed Dec. 3, 1999 (Amerasekera et al., xe2x80x9cElectrostatic Discharge Device and Methodxe2x80x9d).
In general, even good design and fabrication improvement steps are not able to completely eliminate ESD sensitivity of complex circuits. Consequently, predictive modeling at the circuit level has become extremely important since experimental methods require destructive testing, costly failure analysis to determine the effectiveness of a protection scheme, and often a frustrating redesign of the circuit. A first effort in this direction is described in U.S. Pat. No. 5,796,638, issued on Aug. 18, 1998 (Kang et al., xe2x80x9cMethods, Apparatus and Computer Program Products for Synthesizing Integrated Circuits with Electrostatic Discharge Capability and Connecting Ground Rules thereinxe2x80x9d). A software system generates an IC schematic containing power rails and electrical paths interconnecting retrieved circuit elements and I/O pads. The resistances of the electrical paths to the I/O pads are then determined. Lengths and/or widths of the electrical paths and power rails are adjusted to eliminate/correct ground rules faults. The IC schematic is thus updated. The method is inadequate for extracting parasitic devices and considering substrate resistance effects.
Another design and verification effort is described in U.S. Pat. No. 6,086,627, issued on Jul. 11, 2000 (Bass et al., xe2x80x9cMethod of Automated ESD Protection Level Verificationxe2x80x9d). Minimum wire width and maximum resistance constraints are applied to each of the chip""s I/O ports. These constraints are propagated to the design and then verified; power rails are similarly checked. The method is inadequate for extracting parasitic devices and considering substrate resistance effects.
Modeling examples for designing and analyzing ESD protection circuits and detecting ESD design errors have been described in the papers xe2x80x9cModeling MOS Snapback and Parasitic Bipolar Action for Circuit-Level ESD and High Current Simulationsxe2x80x9d (by A. Amerasekera, S. Ramaswamy, M.-C. Chang, and C. Duvvury, Proc. Int. Reliab. Phys. Symp. 1996, pp. 318-326; extensive literature reference list), and xe2x80x9cAn Automated Tool for Detecting ESD Design Errorsxe2x80x9d (by S. Sinha, H. Swaminathen, G. Kadamati, and C. Duvvury, EOS/ESD Symp. 1998, pp. 208-217). In these papers, a system and flow are outlined to check a given IC design for ESD performance. The impact on detecting faulty IC component values and design errors is illustrated by a number of examples. However, contributions and impact of the substrate resistance network are not considered and options for optimizing the circuit parameters are not offered.
In the recent U.S. patent application Ser. No. 60/258,659, filed Dec. 29, 2000 (Ramaswamy et al., xe2x80x9cSemiconductor Device Extractor for Electrostatic Discharge and Latch-up Applicationsxe2x80x9d), a computerized system and method is disclosed for minimizing ESD and latch-up sensitivities in an IC design. This application combines input data from device layout, technology rules and doping profiles in order to extract netlists, element location and substrate resistance, analyze the layout for parasitic device formation. The application outputs lists of ESD- and latch-up sensitive elements and their locations. However, the application cannot simulate an actual ESD event in order to get a quantitative answer about value and location of ESD-sensitive elements. The present invention is related to this patent application.
An urgent need has, therefore, arisen for a coherent, low-cost system and method of quantitatively simulating an ESD event in an IC, while the IC is still in the design stage. The answers should be quantitative, and the system flexible enough for different semiconductor product families and a wide spectrum of design and process variations. Preferably, these innovations should also shorten IC design cycle time.
For quantitatively identifying sensitivities against electrostatic discharge (ESD) and latch-up in an integrated circuit (IC) design (before the actual IC is fabricated), the disclosed computer system and method combine information from the design netlist, the elements model, a safe operating file, and a list of stress simulations, and apply a simulated, quantified ESD event to the design. The observed sensitivities of the design elements to ESD and latch-up are then quantitatively analyzed, critical stress values are judged, and element failures recorded. Finally, element and location lists of sensitivities and failures are output in a specific format.
The present invention is related to high density ICs, especially those to be used at very high frequencies and having high numbers of input/outputs, tight design and layout rules, and a complex flow of fabrication steps. These ICs can be found in many semiconductor device families such as microprocessors, digital signal processors, standard linear and logic products, digital and analog devices, high frequency and high power devices, wireless and both large and small area chip categories. Since the invention aims at designing devices with minimum geometries and high reliability, it supports continually shrinking applications such as cellular communications, pagers, hard disk drives, laptop computers and medical instrumentation.
It is an aspect of the present invention to provide an automated system and method for detecting IC design errors relative to ESD and latch-up. This aspect is achieved by processing a pre-determined ESD event through the design and monitoring quantitatively the susceptibility to ESD failure models.
Another aspect of the present invention is to provide a quantitative and highly flexible system and method. This aspect is achieved by the embodiments of two subsystems of the invention:
A pre-processor drawing inputs from four sources:
a netlist from one of two independent input sources, namely an IC layout file or an IC schematic file;
a model of elements including parasitic, ESD- and latch-up-sensitive elements;
safe circuit operating conditions relative to ESD and latch-up stability; and
customized stress simulation conditions relative to ESD and latch-up applications.
A post-processor operable to
quantitatively analyze the sensitivities of the design elements relative to ESD and latch-up;
critically judge the observed stress values; and
record any observed element failures.
Another aspect of the present invention is to provide the computer system output in specific formats or displays directly useful to circuit designers. This aspect has been achieved by the embodiment of an output generator which creates a report of the observed ESD and latch-up sensitivities including an element list and a location list of the element failures. The output is expressed in a specific format useful to IC designers.
Another aspect of the present invention is to introduce computer concepts which are flexible so that they can be applied to several performance criteria of integrated circuits relative to ESD and latch-ups, and are general so that they can be applied to several generations of products.
These aspects have been achieved by teachings and embodiments of the invention. Various modifications have been successfully employed to satisfy different selections of product geometries, processes and characteristics. The method of the invention provides easy expansion to new IC designs, and easy specialization to customer-specific requirements.
The technical advances represented by the invention, as well as the objects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.